Carbon nanotube semiconductor devices and deterministic nanofabrication methods

ABSTRACT

Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

FIELD OF THE INVENTION

The embodiments of the invention relate to integrated circuit chips,semiconductor devices, transistors, interconnects, and carbon nanotubes.

BACKGROUND INFORMATION

The push toward ever-smaller more highly integrated circuit (IC) andother semiconductor devices places enormous demands on the techniquesand materials used to construct the devices. In general, an integratedcircuit chip is also known as a microchip, a silicon chip, or a chip. ICchips are found in a variety of common devices, such as themicroprocessors in computers, cars, televisions, CD players, andcellular phones. A plurality of IC chips are typically built on asilicon wafer (a thin silicon disk, having a diameter, for example, of300 mm) and after processing the wafer is diced apart to createindividual chips. A 1 cm2 IC chip having feature sizes around of about90 nm can comprise hundreds of millions of components. Currenttechnologies are pushing feature sizes even smaller than 32 nm.Components of IC chips include, for example, transistors such as CMOS(complementary metal-oxide-semiconductor) devices, capacitivestructures, resistive structures, and metal lines that provideelectronic connections between components and external devices.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic diagram illustrating an array of carbon nanotubetransistors.

FIGS. 2A-B provide views of transistor structures employing a carbonnanotube in the channel region.

FIG. 3 is a schematic diagram illustrating an array of carbon nanotubeinterconnect structures.

FIG. 4 provides an additional view of an interconnect structureemploying carbon nanotubes.

FIGS. 5A-D illustrate interconnect structures comprising carbonnanotubes.

FIG. 6 illustrates a method for the deterministic nanofabrication oftransistor structures.

FIG. 7 illustrates a method for the deterministic nanofabrication ofinterconnect structures.

FIG. 8 is a computing device built in accordance with an implementationof the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention provide transistor structures andinterconnect structures that employ carbon nanotubes (CNTs). Furtherembodiments of the invention provide methods of fabricating transistorstructures and interconnect structures that employ carbon nanotubes.Deterministic nanofabrication techniques according to embodiments of theinvention can provide efficient routes for the large-scale manufactureof transistor and interconnect structures for use, for example, inrandom logic and memory circuit applications.

In the case of transistor devices. FIG. 1 provides an array ofstructures that have channel regions comprising carbon nanotubes. Thecomponents shown in FIG. 1 represent a very small section of a typicalIC device which may include many more (or fewer) transistors than thenumber illustrated in FIG. 1 as well as additional devices,interconnections, and components. In FIG. 1, a substrate 105 houses anarray of assembly regions 110 on its surface. Two assembly regions 110are spanned by one or more carbon nanotubes 115. In embodiments of theinvention, the carbon nanotube 115 is a single-walled carbon nanotube.In embodiments of the invention, the carbon nanotube 115 is asemi-conducting carbon nanotube. Assembly regions 110 are regions thatcan exhibit a strong chemical affinity for an end functionalized carbonnanotube which can cause the attachment of the carbon nanotube to theassembly region. In embodiments of the invention, assembly regions 110can be comprised, in their entirety or in a region, of polysilicon ordoped polysilicon and carbon, nitrogen, and oxygen. Dopants include, forexample, boron, phosphorous, antimony, and arsenic. The polysilicon ordoped polysilicon regions can also comprise C═O groups on the surface.The polysilicon or doped polysilicon regions comprising carbon,nitrogen, and oxygen can be located at the interface of the polysiliconor doped polysilicon region and the carbon nanotube 115. In furtherembodiments of the invention, the polysilicon or doped polysilicon cancomprise regions comprising carbon, nitrogen, and oxygen and C═O groupsat the interface of the polysilicon or doped polysilicon region and thecarbon nanotube 115. In further embodiments of the invention, theassembly regions 110 are comprised of a metal or a mixture of metals, M,such as, for example, gold, silver, copper, cobalt, nickel, palladium,and/or platinum. The assembly regions 110 are also comprised, in theirentirety or in a region, of for example, MNiS (a mixture of themetal(s), nickel, and sulfur), MCoS (a mixture of the metal(s), cobalt,and sulfur), and/or MN (a mixture of the metal(s) and nitrogen).Optionally, the assembly regions 110 comprise nanocrystals of metal.Depending on the manufacturing process, there may also optionally be oneor more randomly distributed (occurring in different orientations,numbers, and/or attachment locations) carbon nanotube fragments 117associated with one or more assembly regions 110.

The gate electrode can lie within the region 120 enclosed by a dashedline. In an embodiment of the invention, the gate electrode (not shown)lies below the substrate 105 surface and a gate dielectric (not shown)is disposed between the gate electrode and the carbon nanotube 115. Thegate dielectric can be on some or all of the substrate surface. In anadditional embodiment of the invention, the gate dielectric (not shown)is disposed on carbon nanotubes 115, and the gate electrode (not shown)disposed on the gate dielectric, and the gate region can be described asbeing all around the carbon nanotube 115. The gate dielectric is betweenthe gate electrode and the carbon nanotube 115. In FIG. 1, the sourceand drain regions 125 have been illustrated for one transistorstructure, but have been omitted for clarity of illustration in theother transistor structures.

In embodiments of the invention, the array of assembly regions 110 inFIG. 1 can be described as columns of assembly regions 110. The distancebetween a first metal region 110 in a first column and a secondproximate metal region 110 in a second proximate column is d1. A carbonnanotube 115 bridges a metal region 110 in the first column and theproximate metal region 110 in the second column. The distance betweenproximate assembly regions 110 within a column is d2. A third column ofassembly regions 110 is separated from the second column by a distanced3. A fourth column of assembly regions 110 is separated from the thirdcolumn by a distance d1. A carbon nanotube 115 bridges a metal region110 in the third column and a proximate metal region 110 in the fourthcolumn. Bridging by a carbon nanotube 115 implies that a first end ofthe carbon nanotube 115 contacts a first metal region 110 and a secondend of the carbon nanotube contacts a second metal region 110. Thelength of the carbon nanotube 115 in FIG. 1 is d4. In embodiments of theinvention, the length of the carbon nanotube 115, d4, is approximately(±20%) the same as d1, so that carbon nanotube 115 is capable ofspanning between desired proximate assembly regions 110. Other valuesfor the relative lengths of a carbon nanotube 115 and d1 are alsopossible and depend, in part, on the size of the metal region 110.However, d2 and d3 are not the same as d1 so that the carbon nanotube115 is not capable of spanning between proximate assembly regions 110separated by distances d2 and d3. In embodiments of the invention d2>d1and d3>d1. When d2 is larger than d1 and d3 is larger than d1undesirable electrical shorting can be avoided. In the case of d2>>d1and d3>>d1 additional masking steps (e.g., lithography, etching, andmask removal), as described more fully herein, can be eliminated toreduce manufacturing costs and complexity.

In the case of transistor devices, FIGS. 2A-B provide views ofstructures employing carbon nanotubes in the channel region. In FIG. 2A,a gate electrode 210 and a gate dielectric 215 layer are disposed on asubstrate 205. A carbon nanotube 225 is between source and drain regions230 and 232. In embodiments of the invention, the region 235 surroundingthe carbon nanotube 225 is comprised of a material, such as air or adielectric material. In further embodiments of the invention, the region235 is comprised of a photo patternable (or “photo definable”) low-kdielectric material. The region 235 can be partially comprised of orcomprised in its entirety of a photo patternable low-k dielectricmaterial. The device of FIG. 2A can also function as a switch orinterconnect.

In FIG. 2B, a carbon nanotube 225 is between source and drain regions230 and 232. A gate dielectric layer 215 is disposed on carbon nanotube225 and a gate electrode 210 is disposed on the gate dielectric layer215. The gate dielectric layer 215 wraps around the carbon nanotube 225.The gate electrode 210 wraps around the gate dielectric layer 215. In anembodiment of the invention, the gate dielectric layer 215 is comprisedof a high-k dielectric material. Wrap-around gate materials can bedeposited, for example, by atomic layer deposition (ADL) processes. Inembodiments of the invention, in FIGS. 2A-B, the carbon nanotube 225 isa semi-conducting carbon nanotube. In embodiments of the invention, thecarbon nanotube 225 is a single-walled carbon nanotube. In FIGS. 2A-B,the ends of the carbon nanotube 225 contact assembly regions 240.Assembly regions 240 are regions that can exhibit a strong chemicalaffinity for an end functionalized carbon nanotube which can cause theattachment of the carbon nanotube to the assembly region. In embodimentsof the invention, assembly regions 240 can be comprised, in theirentirety or in a region, of polysilicon or doped polysilicon and carbon,nitrogen, and oxygen. Dopants include, for example, boron, phosphorous,antimony, and arsenic. The polysilicon or doped polysilicon regions canalso comprise C═O groups on the surface. The polysilicon or dopedpolysilicon regions comprising carbon, nitrogen, and oxygen can belocated at the interface of the polysilicon or doped polysilicon regionand the carbon nanotube 225. In further embodiments of the invention,the polysilicon or doped polysilicon can comprise regions comprisingcarbon, nitrogen, and oxygen and C═O groups at the interface of thepolysilicon or doped polysilicon region and the carbon nanotube 225. Infurther embodiments of the invention, the assembly regions 240 arecomprised of a metal or mixture of metals, M, such as, for example,gold, silver, copper, cobalt, nickel, palladium, and/or platinum. Theassembly regions 240 are also comprised, in their entirety or in aregion, of for example, MNiS (a mixture of the metal, nickel, andsulfur), MCoS (a mixture of the metal, cobalt, and su(fur), and/or MN (amixture of the metal and nitrogen). Optionally, the assembly regions 240comprise nanocrystals of metal.

Gate dielectric materials include, for example, insulating materials,such as, silicon dioxide (SiO2), oxynitride (SiOxNy), silicon nitride(Si3N4), and/or a high-k dielectric materials. In general, a high-kdielectric is a dielectric material having a dielectric constant greaterthan that of SiO2. Exemplary high-k dielectric materials include hafniumdioxide (HfO2), hafnium silicon oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium dioxide (ZrO2), zirconium silicon oxide,titanium dioxide (TiO2), tantalum pentaoxide (Ta2O5), barium strontiumtitanium oxide, barium titanium oxide, strontium titanium oxide, yttriumoxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate,and other materials known in the semiconductor art.

Gate electrode materials include, for example, materials such as Ti, W,Ta, Al, and alloys thereof, and alloys with rare earth elements, such asEr, Dy or noble metals such as Pt, Ru, Pd, and Co, Ir, and alloysthereof, and nitrides such as TaN, TiN, and VN. Materials for sourcesand/or drains include, for example, Si, carbon doped Si, and phosphorusdoped Si, SiGe, Ge, and semiconductors (i.e., compound semiconductormaterials comprising elements from Groups III and V of the periodictable).

FIG. 3 illustrates an array of carbon nanotube interconnect structures.The components shown in FIG. 3 represent a very small section of atypical IC device which may include many more (or fewer) transistorsthan the number illustrated in FIG. 3 as well as additional devices,interconnections, and components. In FIG. 3, a substrate 305 houses anarray of assembly regions 310 on its surface. Two assembly regions 310are spanned by one or more carbon nanotubes 315. Assembly regions 310are regions that can exhibit a strong chemical affinity for an endfunctionalized carbon nanotube which can cause the attachment of thecarbon nanotube to the assembly region. In embodiments of the invention,the carbon nanotube 315 is a single-walled carbon nanotube. Inembodiments of the invention, the carbon nanotube 315 is a metallic(conducting) carbon nanotube. In embodiments of the invention, assemblyregions 310 can be comprised, in their entirety or in a region, ofpolysilicon or doped polysilicon and carbon, nitrogen, and oxygen.Dopants include, for example, boron, phosphorous, antimony, and arsenic.The polysilicon or doped polysilicon regions can also comprise C═Ogroups on the surface. The polysilicon or doped polysilicon regionscomprising carbon, nitrogen, and oxygen can be located at the interfaceof the polysilicon or doped polysilicon region and the carbon nanotube315. In further embodiments of the invention, the polysilicon or dopedpolysilicon can comprise regions comprising carbon, nitrogen, and oxygenand C═O groups at the interface of the polysilicon or doped polysiliconregion and the carbon nanotube 115. In further embodiments of theinvention, the assembly regions 310 are comprised of a metal or mixtureof metals, M, such as, for example, gold, silver, copper, cobalt,nickel, palladium, platinum, and/or alloys thereof. The assembly regions310 can also be comprised, in their entirety or in a region, of MNiS (amixture of the metal, nickel, and sulfur), MCoS (a mixture of the metal,cobalt, and sulfur), and/or MN (a mixture of the metal and nitrogen).Optionally, the assembly regions 310 comprise nanocrystals of metal.Depending on the manufacturing process, there may also optionally be oneor more randomly distributed (occurring in different orientations,numbers, and/or attachment locations) carbon nanotube fragments 317associated with one or more assembly regions 310.

In embodiments of the invention, the array of assembly regions 310 inFIG. 3 can be described as columns of assembly regions 310. The distancebetween a first metal region 310 in a first column and a secondproximate metal region 310 in a second proximate column is d1. A carbonnanotube 315 spans a metal region 310 in the first column and theproximate metal region 310 in the second column. The distance betweenproximate assembly regions 310 within a column is d2. A third column ofassembly regions 310 is separated from the second column by a distanced3. A fourth column of assembly regions 310 is separated from the thirdcolumn by a distance d1. A carbon nanotube 315 spans a metal region 310in the third column and a proximate metal region 310 in the fourthcolumn. Spanning by a carbon nanotube 315 implies that a first end ofthe carbon nanotube 315 contacts a first metal region 310 and a secondend of the carbon nanotube contacts a second metal region 310. Thelength of the carbon nanotube 315 in FIG. 3 is d4. In embodiments of theinvention, the length of the carbon nanotube 315, d4, is approximately(±20%) the same as d1, so that a carbon nanotube 315 is capable ofspanning between desired proximate assembly regions 310. Other valuesfor the relative lengths of a carbon nanotube 315 and d1 are alsopossible and depend, in part, on the size of the metal region 310.However, d2 and d3 are not the same as d1 so that the carbon nanotube315 is not capable of spanning between proximate assembly regions 315separated by distances d2 and d3, in embodiments of the invention d2>d1and d3>d1. When d2 is larger than d1 and d3 is larger than d1undesirable electrical shorting can be avoided. In the case of d2>>d1and d3>>d1 additional masking steps (e.g., lithography, etching, andmask removal), as described more fully herein, can be eliminated toreduce manufacturing costs and complexity.

FIG. 4 illustrates a carbon nanotube interconnect structure. In FIG. 4,a substrate 405 comprises conducting vias 410. The substrate 405 iscomprised of a dielectric material. In embodiments of the invention,conducting vias 410 are comprised of a metal, such as copper. Twoassembly regions 415 are spanned by one or more carbon nanotubes 425. Inembodiments of the invention, the carbon nanotube 425 is a single-walledcarbon nanotube. In embodiments of the invention, the carbon nanotube425 is a metallic carbon nanotube. Assembly regions 415 are regions thatcan exhibit a strong chemical affinity for an end functionalized carbonnanotube which can cause the attachment of the carbon nanotube to theassembly region. In embodiments of the invention, assembly regions 415can be comprised, in their entirety or in a region, of polysilicon ordoped polysilicon and carbon, nitrogen, and oxygen. Dopants include, forexample, boron, phosphorous, antimony, and arsenic. The polysilicon ordoped polysilicon regions can also comprise C═O groups on the surface.The polysilicon or doped polysilicon regions comprising carbon,nitrogen, and oxygen can be located at the interface of the polysiliconor doped polysilicon region and the carbon nanotube 425. In furtherembodiments of the invention, the polysilicon or doped polysilicon cancomprise regions comprising carbon, nitrogen, and oxygen and C═O groupsat the interface of the polysilicon or doped polysilicon region and thecarbon nanotube 115. In further embodiments of the invention, theassembly regions 415 are comprised of a metal or a mixture of metals, M,such as, for example, gold, silver, copper, cobalt, nickel, palladium,platinum or alloy materials thereof. The assembly regions 415 are alsocomprised, in their entirety or in a region, of for example, MNiS (amixture of the metal, nickel, and sulfur), MCoS (a mixture of the metal,cobalt, and sulfur), and/or MN (a mixture of the metal and nitrogen).Optionally, the assembly regions 415 comprise nanocrystals of metal. Thecarbon nanotube 425 interconnect can be covered in a dielectric material430. The dielectric material 430 can be a material such as silicondioxide, a carbon-doped oxide (CDO), a fluorocarbon material (CFx), ahydrocarbon material (CHx), a carbosilane material, an oxycarbosilanematerial, a silicon carbide, or a silicon nitride (any of which may beporous). In embodiments of the invention, a region of the dielectricmaterial 430 proximate to the carbon nanotube 415 is comprised of aphoto patternable (low-k) dielectric material.

FIGS. 5A-D illustrate carbon nanotube semiconductor interconnectcontact/via structures. In FIG. 5A an insulating layer 510 is disposedon substrate 505. Dielectric layer 510 comprises vias 515. Inembodiments of the invention, the dielectric layer 510 is comprised of anegative photo-definable spin-on photoresist. Other dielectric materialsare also possible, such as, for example, silicon dioxide, a carbon-dopedoxide (CDO), a fluorocarbon material (CFx), a hydrocarbon material(CHx), a carbosilane material, an oxycarbosilane materials, a siliconcarbide, or a silicon nitride (any of which may he porous). Assemblyregions 520 are disposed at an end of the via 515 on the substrate 505.Assembly regions 520 are regions that can exhibit a strong chemicalaffinity for an end functionalized carbon nanotube which can cause theattachment of the carbon nanotube to the assembly region. In embodimentsof the invention, assembly regions 520 can be comprised, in theirentirety or in a region, of polysilicon or doped polysilicon and carbon,nitrogen, and oxygen. Dopants include, for example, boron, phosphorous,antimony, and arsenic. The polysilicon or doped polysilicon regions canalso comprise C═O groups on the surface. The polysilicon or dopedpolysilicon regions comprising carbon, nitrogen, and oxygen can belocated at the interface of the polysilicon or doped polysilicon regionand the carbon nanotube 525. In further embodiments of the invention,the polysilicon or doped polysilicon can comprise regions comprisingcarbon, nitrogen, and oxygen and C═O groups at the interface of thepolysilicon or doped polysilicon region and the carbon nanotube 115. Infurther embodiments of the invention, the assembly regions 520 arecomprised of a metal or mixture of metals, M, such as, for example,gold, silver, cobalt, palladium, platinum, copper, nickel, or alloymaterials thereof. The assembly regions 520 are also comprised, in theirentirety or in a region, of for example, MNiS (a mixture of the metal,nickel, and sulfur), MCoS (a mixture of the metal, cobalt, and sulfur),and/or MN (a mixture of the metal and nitrogen). Optionally, theassembly regions 520 comprise nanocrystals of metal. One or more carbonnanotubes 525 are located in the via 515 and span the distance betweenthe metal region 520 and an electrical interconnect 530 so that one endof a carbon nanotube 525 contacts the metal region 520 and the other endcontacts the electrical interconnect 530. Electrical interconnect 530can be a trench. Inside the via 515, there can be one carbon nanotube525 or a bundle of carbon nanotubes 525. In embodiments of the inventionthe bundle can comprise, for example, from 2 to 2000 carbon nanotubes525. In embodiments of the invention, the carbon nanotube 525 is asimile-walled carbon nanotube. In embodiments of the invention, thecarbon nanotube 525 is a metallic carbon nanotube (a conducting carbonnanotube). The electrical interconnect 530 is comprised, for example, ofa metal, such as, copper, aluminum, silver, and/or gold. In embodimentsof the invention, the electrical interconnect is comprised of copper.

Elements of the semiconductor interconnect structures of FIG. 5B aresimilar to those shown and described with respect to FIG. 5A. However,FIG. 5B includes an additional liner layer 535 between the electricalinterconnect 530 and the dielectric layer 510. Although not shown inFIG. 5B, the liner layer 535 can also be recessed into the via 515. Inembodiments of the invention, the liner layer 535 comprises Ta, TaN, Ti,TiN, WN, VN, Co, manganese oxide, manganese silicate, Ru doped with P,and/or Ru doped with B. Other materials are also possible. Inembodiments of the invention, the liner layer can serve as anelectromigration barrier.

Elements of the semiconductor interconnect structures of FIG. 5C aresimilar to those shown and described with respect to FIG. 5A. However,FIG. 5C includes a dielectric fill layer 540 in via 515. The dielectricfill layer 540 can partially or fully fill the via 515. In embodimentsof the invention, the dielectric fill layer 540 comprises a low-kmaterial, such as a spin-on low-k dielectric or a photodefinable low-kdielectric, although other materials are also possible. Elements of thesemiconductor interconnect structures of FIG. 5D are similar to those ofFIG. 5C. However, FIG. 5D includes an additional liner layer 535 betweenthe electrical interconnect 530 and the dielectric layer 510 and thedielectric fill layer 540. In embodiments of the invention, the linerlayer 535 comprises Ta, TaN, Ti, TiN, WN, VN, Co, manganese oxide,manganese silicate, Ru doped with P, and/or Ru doped with B. Othermaterials are also possible. In embodiments of the invention, the linerlayer can serve as an electromigration barrier.

The substrates (or lower layers) 505 can comprise other vias, lines,interconnects, and/or devices (not shown) in electrical contact with theassembly regions 520 and other devices and/or structures that are partof the monolithic IC chip which the interconnect structures of FIGS.5A-D are a part.

FIG. 6 illustrates a method for forming an array of structures that haveregions comprising carbon nanotubes. In FIG. 6, Structure (i), asubstrate 605 comprises an array of assembly regions 610. The substrate605 can comprise gate dielectric and gate electrode regions, such as,for example those shown with respect to FIGS. 1 and 2. The array ofassembly regions 610 can be created, for example, through patterningusing top down lithography techniques or bottom-up self-assemblytechniques. The array of assembly regions 610 have a geometric layout onthe substrate 605 such that carbon nanotubes having a monodisperselength can only bridge two assembly regions 610 between which aconnection is desired, such as, for example, the layouts described withrespect to FIGS. 1 and 3. The assembly regions 610 are comprised of amaterial that is capable of or a material that is chemicallyfunctionalized to be capable of causing the assembly regions 610 todirect the assembly of spanning carbon nanotubes 615. The assemblyregions 610 can be comprised of a metal or mixture of metals, M, suchas, for example, gold, silver, copper, cobalt, nickel, palladium,platinum, or alloy materials thereof. The assembly regions 610 canalternatively be comprised of polysilicon or doped polysilicon that issurface functionalized with, for example, carboxylic acid groups.Dopants include, for example, boron, phosphorous, antimony, and arsenic.The carbon nanotubes 615 exhibit monodisperse lengths and are chemicallyend functionalized in a manner that guides assembly of the array ofstructures comprising bridged carbon nanotubes 615 on substrate 605.Semiconducting carbon nanotubes 615 having desired monodisperse lengthscan be prepared using selective growth techniques or post-syntheticseparation techniques. Post-synthetic separation techniques includepurification techniques such as density gradient ultracentrifugation.Pentagonal and hexagonal defects in single-walled carbon nanotubestructures localized primarily on the ends of the tubes can serve asnucleation sites for selective area atomic layer deposition (ALD) offunctionalization materials. For example, atomic layer deposition ofNi3S2, NiS2, and/or Co9S8 onto the end regions of a carbon nanotube canbe used to direct binding of the carbon nanotube ends to assemblyregions comprised of late transition metals, such as, Ag, Au, and/or Cu.Atomic layer deposition can deposit a few layers of a material such asNi3S2, NiS2, and/or Co9S8 onto the ends of the carbon nanotubes. Atomiclayer deposition of carbon nanotubes can be carried out in a rotary ALDreactor. Alternately, carbon nanotubes can be selectively endfunctionalized using vapor phase or solution phase reactions to endfunctionalize the carbon nanotubes with amine groups. Amine terminatedcarbon nanotubes can be used to direct binding to the carboxylic acidgroups of the polysilicon or doped polysilicon assembly regions. Aminefunctionalization on the end regions of a carbon nanotube can also beused to direct binding of the carbon nanotube ends to assembly regionscomprised of late transition metals. Structure (ii) of FIG. 6 is formedby, for example, applying end functionalized carbon nanotubes havingmonodisperse lengths dispersed in a solvent or mixture of solvents tothe surface of substrate 605. Optionally, the solvent or mixture ofsolvents comprises surfactants. Also, optionally, the solutioncomprising dispersed end functionalized carbon nanotubes can be agitatedto facilitate the fluidic self-assembly process in which thefunctionalized ends of the carbon nanotubes attach to the assemblyregions 610. The carbon nanotubes can form useful structures in whichthey bridge two proximate assembly regions 610 and can formnon-functional structures (carbon nanotube 117) in which one or no endsare in contact with assembly regions 610. Following fluidicself-assembly, the substrate 605 is rinsed to remove the majority ofcarbon nanotubes not interacting with assembly regions 610. The carbonnanotubes 615 can be optionally sintered in place by using a thermalannealing process. In embodiments of the invention, the thermal annealoccurs at less than 450° C. The annealing process can optionally befacilitated by the use of UV (ultra violet) or other electromagneticradiation.

FIG. 6, Structure (iii) is formed by depositing a patternable dielectricmaterial 620, such as a photo patternable low-k dielectric material, onthe surface of the substrate 605, patterning the dielectric material620, and partially removing dielectric material 620 according to thepattern. In embodiments of the invention, the patternable dielectricmaterial 620 can also be a chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD), high density plasma chemicalvapor deposition (HDP CVD), or spin on material, such as a photoresist,a other curable material with a composition sufficiently different fromthat of the carbon nanotubes such that exposed carbon nanotubes orcarbon nanotube segments 617 can be removed in the presence ofdielectric material 620, or other curable material with a compositionsufficiently different from that of the carbon nanotubes such that aselective etch process can remove the material 620 preferentiallyleaving carbon nanotubes 615 intact and such that exposed carbonnanotubes or carbon nanotube segments 617 can be removed in the presenceof dielectric material 620. The undesired dielectric material can beremoved, for example, through development of the photodefinabledielectric, through a subtractive etch process for a conventionaldielectric material, or an ash for a photoresist material. Resultingpatterned regions 620 comprising a dielectric material protectively maskcarbon nanotubes 615 that are spanning assembly regions 610. Structure(iv) is then formed by partially or fully removing exposed carbonnanotubes 617 (in which one or no ends are in contact with assemblyregions 610), by for example, ashing them away. Ashing to remove exposedcarbon nanotubes can be perforated, for example, at a temperature lessthan 250° C. As mentioned above with respect to FIGS. 1 and 3, inembodiments where d2>>d1 and d3>>d1 additional masking processes shownwith respect to Structures (iii) and (iv) of FIG. 6 can be eliminated toreduce manufacturing costs and complexity. Additional elements of thetransistor structure, such as sources, drains, and gate regions can beformed using standard semiconductor processing techniques. Inembodiments of the invention, the dielectric material 620 remains in thefinal device structure. In further embodiments of the invention, thedielectric material 620 is photo patternable low-k dielectric materialand remains in the final device structure. The dielectric material 620can also be removed.

FIG. 7 illustrates a method for forming an array of contact/viainterconnect structures comprising carbon nanotubes. In FIG. 7,Structure (i), a substrate 705 comprises an array of assembly regions710. The substrate 705 can comprise other vias, lines, interconnects,and/or devices (not shown) in electrical contact with the assemblyregions 710 and other devices and/or structures that are part of themonolithic IC chip of which the interconnect structures of FIG. 7 are apart. Assembly regions 710 are capable of attaching to endfunctionalized carbon nanotubes. In alternate embodiments, the assemblyregions 710 can be placed on the substrate 705 after patterning the vias725 through the dielectric material 715.

Structure (ii) of FIG. 7 is formed by depositing a dielectric material715 on the substrate and patterning the dielectric material 715 tocreate vias 725 and trenches 720. The dielectric material 715 can be,for example, a photo patternable dielectric material (either spin-on orCVD) or any other dielectric material that can be patterned and etched.The assembly regions 710 are comprised of a material that is capable ofor a material that is chemically functionalized to be capable of causingthe assembly regions 710 to direct the attachment of carbon nanotubes730 to metal region 710 inside vias 725. The assembly regions 710 can becomprised of a metal or mixture of metals, M, such as, for example,gold, silver, copper, cobalt, nickel, palladium, and/or platinum. Thecarbon nanotubes 730 are chemically end functionalized in a manner thatguides assembly of structures comprising carbon nanotubes 730 in vias725. Conducting carbon nanotubes 730 having desired lengths can beprepared using selective growth techniques or post-synthetic separationtechniques. Post-synthetic separation techniques include purificationtechniques such as density gradient ultracentrifugation. Pentagonal andhexagonal defects in single-walled carbon nanotube structures localizedprimarily on the ends of the tubes can serve as nucleation sites forselective area atomic layer deposition (ALD) of functionalizationmaterials. For example, atomic layer deposition of Ni3S2, NiS2, and/orCo9S8 onto the end regions of a carbon nanotube can be used to directbinding of the carbon nanotube ends to assembly regions comprised oflate transition metals, such as, Ag, Au, and/or Cu. Atomic layerdeposition can deposit a few layers of a material such as Ni3S2, NiS2,and/or Co9S8 onto the ends of the carbon nanotubes. Alternately, carbonnanotubes can be selectively end functionalized using vapor phase orsolution phase reactions to end functionalize the carbon nanotubes withamine groups. Amine terminated carbon nanotubes can be used to directbinding to the carboxylic acid groups of the polysilicon or dopedpolysilicon assembly regions. Amine functionalization on the end regionsof a carbon nanotube can also be used to direct binding of the carbonnanotube ends to assembly regions comprised of late transition metals.Structure (iii) of FIG. 7 can be formed by, for example, applying endfunctionalized carbon nanotubes having monodisperse lengths dispersed ina solvent or mixture of solvents to the surface of Structure (ii).Optionally, the solvent Or mixture of solvents comprises surfactants.Also, optionally, the solution comprising dispersed end functionalizedcarbon nanotubes can be agitated to facilitate the fluidic self-assemblyprocess in which the functionalized ends of the carbon nanotubes attachto the assembly regions 710. In embodiments of the invention the carbonnanotubes 730 are a single carbon nanotube or a bundle of carbonnanotubes 730. A bundle of carbon nanotubes can comprise from 2 to 2000carbon nanotubes. In further embodiments, the carbon nanotubes 730 aremetallic and/or single-walled carbon nanotubes. An electrical connectionis formed between the carbon nanotube 730 and the metal region 710.

In FIG. 7, Structure (iv) is manufactured by depositing a conductingmaterial 735 into trenches 720. The conducting material 735 is, forexample, a metal, such as, copper, aluminum, gold, and/or silver,although other materials are also possible. In embodiments of theinvention, the conducting material 735 is copper and the depositionoccurs through first depositing a seed layer of copper by, for examplePVD, CVD, or ALD, and then through an electrochemical depositionprocess. Optionally, before the conducting material 735 is deposited,the via 725 is partially or fully filled with a dielectric material 740.The dielectric material 740 can be a spin-on flowable dielectricmaterial, such as, for example, silicon oxide, a carbon-doped oxide(CDO), a fluorocarbon material (CFx), a hydrocarbon material (CHx), acarbosilane material, an oxycarbosilane material, a silicon carbide, ora silicon nitride (any of which may be porous). This material can bepolished or edged back to expose the tops of the carbon nanotubes 730.Also optionally, before the conducting material 735 is deposited, andafter an optional dielectric material 740 is deposited in the vias 725and etched back, a metal liner layer 745 can be deposited into trenches720. The surface of the structure is then chemically/mechanicallypolished to remove unwanted (overburden) liner layer and/or conductingmaterial from the surface.

In general, carbon nanotubes are fullerene-related structures consistingof cylindrical nanomeric structures of carbon atoms arranged in ahexagonal lattice. Carbon nanotubes can he single-walled or multi-walled(concentric). In embodiments of the invention, the carbon nanotubes aresingle-walled carbon nanotubes. Carbon nanotubes can be formed, forexample, at graphite electrodes during the arc-evaporation of carbon.Single-walled carbon nanotubes can be formed at graphite electrodescontaining metals such as cobalt.

Typical dielectric materials used for dielectric layers, features,and/or interlayer dielectrics (ILD) include silicon dioxide, low-kdielectric materials, and photoresists. Additional dielectric materialsthat may be used include, carbon doped oxides (CDOs), silicon nitrides,silicon oxynitrides, silicon carbides, fluorocarbon (CFx) materials(such as films made from polytetrafluoroethylene, or films formed fromPECVD deposition of fluorocarbon precursors (like perfluorocyclobutane)or spin-on fluorocarbon materials), hydrocarbon materials (CHx),fluorosilicate glass (FSG), and/organosilicates such as silsesquioxane,siloxane, or organosilicate glass. Other dielectric materials includephoto patternable low-k dielectric materials. Photo patternablematerials can have a chemical composition described above, but alsoeither have photoactive groups attached to the backbone to changepolarity for solvation or include a photoactive compound (such as, aphoto acid generator, photo base generator, photo lewis acid generator,etc.) that, when activated by electromagnetic radiation, enable thebackbone material to crosslink into a solid network (negative tone) orcause the backbone to degrade so that it can be washed away (positivetone) The dielectric layer may include pores to further reduce thedielectric constant.

Implementations of the invention are housed on a substrate, such as asemiconductor substrate. Substrate surfaces on which transistor andinterconnect structures according to embodiments of the invention can beformed include, for example. H-terminated silicon, silicon dioxide,silicon, silicon germanium, a group III-V (or a group 13-15 inadditional periodic table column numbering schemes) compoundsemiconductor, a main-group oxide, a metal, and/or a binary or mixedmetal oxide. The substrate on which implementations of the invention arehoused can be part of an IC chip. Layers and layers comprising devicescan also he described as the substrate or part of the substrate on whichembodiments of the invention are fabricated and housed. The substratebase on which semiconductor devices (IC chips) are built is typically asemiconductor wafer. The base substrate on which an IC chip is built istypically a silicon wafer, although embodiments of the invention are notdependent on the type of substrate used. The substrate could also becomprised of germanium, indium antimonide, lead telluride, indiumarsenide, indium phosphide, gallium arsenide, gallium antimonide, and/orother group III-V materials either alone or in combination with siliconor silicon dioxide or other insulating materials

Devices illustrated herein may comprise additional structures, such asinsulating layers enclosing devices, metal trenches and vias connectingsources and drains to other components, and other additional layersand/or devices. Components illustrated as one layer for simplicity, cancomprise a plurality of layers of the same or a different materialdepending, for example, on the manufacturing processes employed inconstructing the device and the desired properties of the device.

FIG. 8 illustrates a computing device 1000 in accordance with animplementation of the invention. The computing device 1000 houses amotherboard 1002. The motherboard 1002 may include a number ofcomponents, including but not limited to a processor 1004 and at leastone communication chip 1006. The processor 1004 is physically andelectrically coupled to the motherboard 1002. In some implementationsthe at least one communication chip 1006 is also physically andelectrically coupled to the motherboard 1002.

Depending on its applications, computing device 1000 may include othercomponents that may or may not he physically and electrically coupled tothe motherboard 1002. These other components include, but are notlimited to, volatile memory (e.g., DRAM), non-volatile memory (e.g.,ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

The communication chip 1006 enables wireless communications for thetransfer of data to and from the computing device 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 1006 may implementany of a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 1000 may include a plurality ofcommunication chips 1006. For instance, a first communication chip 1006may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 1006 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing device 1000 includes an integratedcircuit die packaged within the processor 1004. In some implementationsof the invention, the integrated circuit die of the processor includesone or more devices, such as transistors and/or interconnects comprisingcarbon nanotubes, in accordance with implementations of the invention.Implementations of the invention are useful, for example, for powerdelivery and signaling functions within the chip. The term “processor”can refer to any device or portion of a device that processes electronicdata from registers and/or memory to transform that electronic data intoother electronic data that may be stored in registers and/or memory.Cache memory can be located on a same processor chip.

The communication chip 1006 also includes an integrated circuit diepackaged within the communication chip 1006. In accordance with anotherimplementation of the invention, the integrated circuit die of thecommunication chip includes one or more devices, such as transistors ormetal interconnects comprising carbon nanotubes, in accordance withimplementations of the invention.

In further implementations, another component housed within thecomputing device 1000 may contain an integrated circuit die thatincludes one or more devices, such as transistors or metal interconnectscomprising carbon nanotubes, in accordance with implementations of theinvention.

In various implementations, the computing device 1000 may be a laptop, anetbook, a notebook, a smartphone, a tablet, a personal digitalassistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer,a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 1000 may be any other electronic device that processes data.

Persons skilled in the relevant art appreciate that modifications andvariations are possible throughout the disclosure as are substitutionsfor various components shown and described. Reference throughout thisspecification to “one embodiment” or “an embodiment” means that aparticular feature, structure, material, or characteristic described inconnection with the embodiment is included in at least one embodiment ofthe invention, but does not necessarily denote that they are present inevery embodiment. Furthermore, the particular features, structures,materials, or characteristics disclosed in the embodiments may becombined in any suitable manner in one or more embodiments. Variousadditional layers and/or structures may be included and/or describedfeatures may be omitted in other embodiments.

We claim:
 1. A structure comprising, a substrate having a surface, at least two assembly regions disposed on the substrate surface, wherein the assembly regions comprise a first metal and a second substance that is selected from the group consisting of sulfur, nitrogen and combinations thereof, a carbon nanotube wherein the carbon nanotube has ends and wherein a first end is in contact with a first assembly region and a second end is in contact with a second assembly region, and source and drain regions wherein the source region is in contact with a first end of the one or more carbon nanotubes and the drain region is in contact with the second end of the one or more carbon nanotubes.
 2. The device of claim 1 wherein the first metal is selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 3. The device of claim 1 wherein the assembly region additionally comprises a second metal that is different from the first metal selected from the group consisting of nickel and cobalt.
 4. The device of claim 1 wherein the substrate additionally comprises a gate dielectric region and a gate electrode region wherein the gate dielectric region is proximate to the one or more carbon nanotubes and the gate dielectric region is between the one or more carbon nanotubes and the gate electrode region.
 5. The device of claim 1 wherein a gate dielectric material is disposed on the carbon nanotube and a gate electrode is disposed on the gate dielectric material.
 6. The device of claim 1 wherein the nanotube is a single-walled semiconducting carbon nanotube.
 7. The device of claim 1 wherein a photo patternable low-k dielectric material is disposed on the carbon nanotube.
 8. A structure comprising, a substrate having a surface, an array of assembly regions on the substrate surface, wherein the array comprises at least two columns of assembly regions, wherein a column of assembly regions comprises at least two assembly regions, wherein a first column of assembly regions is separated from the second column of assembly regions by a first distance, wherein a assembly regions within a column are separated from a nearest proximate assembly region by a second distance, and wherein the first distance is not the same as the second distance, at least two carbon nanotubes wherein a first and a second carbon nanotube have ends, wherein a first end of the first carbon nanotube is in contact with a first assembly region in the first column and a second end of the first carbon nanotube is in contact with a second proximate assembly region in the second column, and wherein a first end of a second carbon nanotube is in contact with a third assembly region in the first column and a second end of the second carbon nanotube is in contact with a fourth proximate assembly region in the second column, and source and drain regions wherein a first source region is in contact with the first end of the first carbon nanotube, a second source region is in contact with the first end of the second carbon nanotube, a first drain region is in contact with a second end of the first carbon nanotube, and a second drain region is in contact with the second end of the second carbon nanotube.
 9. The device of claim 8 wherein the assembly regions comprise polysilicon or doped polysilicon and carbon, nitrogen, and oxygen.
 10. The device of claim 8 wherein the assembly regions comprise a metal and a second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof.
 11. The device of claim 8 wherein the assembly regions comprise a first metal selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 12. The device of claim 11 wherein the assembly regions comprise a second metal that is different from the first metal and selected from the group consisting of nickel and cobalt.
 13. The device of claim 8 wherein the substrate additionally comprises a first and a second gate dielectric region and a first and second gate electrode region wherein the first gate dielectric region is proximate to the first carbon nanotube, the second gate dielectric region is proximate to the second carbon nanotube, the first gate dielectric regions is between the first carbon nanotube and the first gate electrode region, and the second gate dielectric region is between the second carbon nanotube and the second gate electrode region.
 14. The device of claim 8 wherein the carbon nanotubes are single-walled semiconducting carbon nanotubes.
 15. The device of claim 8 wherein a gate dielectric material is disposed on the first and the second carbon nanotube and a gate electrode is disposed on the gate dielectric material.
 16. The device of claim 8 wherein a photo patternable low-k dielectric material is disposed on the carbon nanotube.
 17. A structure comprising, a substrate having a surface wherein the surface has a dielectric material disposed thereon, a via in the dielectric material, an assembly region disposed on the substrate surface at a first end of the via, wherein the assembly region comprises a first metal undo second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof, at least one carbon nanotube wherein the at least one carbon nanotube has ends, wherein one end of the at least one carbon nanotube is in contact with the assembly region and another end of the carbon nanotube is proximate to a second end of the via that is opposite to the first end of the via, a conducting region disposed at the second end of the via and in electrical contact with the carbon nanotube.
 18. The device of claim 17 wherein the at least one carbon nanotube is a bundle of carbon nanotubes.
 19. The device of claim 17 wherein the first metal is selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 20. The device of claim 19 wherein the metal region comprises a second metal selected from the group consisting of nickel and cobalt.
 21. The device of claim 17 wherein the at least one carbon nanotube is a single-walled metallic carbon nanotube.
 22. The device of claim 17 additionally comprising a liner layer between the conducting region and the carbon nanotube.
 23. A computing device comprising, a motherboard, a communication chip mounted on the motherboard, and a processor mounted on the motherboard, the processor comprising a transistor, the transistor comprising: a substrate having a surface, at least two assembly regions disposed on the substrate surface, wherein the assembly regions comprise a first metal and a second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof, a carbon nanotube wherein the carbon nanotube has ends and wherein a first end is in contact with a first assembly region and a second end is in contact with a second assembly region, and source and drain regions wherein the source region is in contact with a first end of the one or more carbon nanotubes and the drain region is in contact with the second end of the one or more carbon nanotubes.
 24. The device of claim 23 wherein the first metal is selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 25. The device of claim 24 wherein the assembly region additionally comprises a second metal that is different from the first metal and is selected from the group consisting of nickel and cobalt.
 26. The device of claim 23 wherein a gate dielectric material is disposed on the carbon nanotube and a gate electrode is disposed on the gate dielectric material.
 27. The device of claim 23 wherein a photo patternable low-k dielectric material is disposed on the carbon nanotube.
 28. A computing device comprising, a motherboard, a communication chip mounted on the motherboard, and a processor mounted on the motherboard, the processor comprising a transistor, the transistor comprising: a substrate having a surface wherein the surface has a dielectric material disposed thereon, a via in the dielectric material, an assembly region disposed on the substrate surface at a first end of the via, wherein the assembly region comprises a first metal undo second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof, at least one carbon nanotube wherein the carbon nanotube has ends, wherein one end of the carbon nanotube is in contact with the assembly region and another end of the carbon nanotube is proximate to a second end of the via that is opposite to the first end of the via, a conducting region in electrical contact with the carbon nanotube disposed at the second end of the via.
 29. The device of claim 28 wherein the at least one carbon nanotube is a bundle of carbon nanotubes.
 30. The device of claim 28 wherein the first metal is selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 31. The device of claim 30 wherein the assembly region additionally comprises a second metal that is different from the first metal and is selected from the group consisting of nickel and cobalt.
 32. A method of forming an array of carbon nanotubes comprising: providing a substrate having a surface and an array of assembly regions on the substrate surface, wherein the array comprises at least two columns of assembly regions, wherein a column of assembly regions comprises at least two assembly regions, wherein a first column of assembly regions is separated from the second column of assembly regions by a first distance, wherein a assembly regions within a column are separated from a nearest proximate assembly region by a second distance, and wherein the first distance is less than the second distance, applying end functionalized carbon nanotubes to the substrate surface wherein the end functionalized carbon nanotubes are capable of bridging between an assembly region in the first column and a proximate assembly region in the second column but are not capable of bridging between two proximate assembly regions in the first column or two proximate assembly regions in the second column, under conditions that allow the end functionalized carbon nanotubes to form bridging structures between an assembly region in the first column and a proximate assembly region in the second column, attaching the bridging end functionalized carbon nanotubes to the assembly regions, and removing any end functionalized carbon nanotubes that are not attached.
 33. The method of claim 32 also comprising depositing a photo patternable low-k dielectric material onto the substrate surface, patterning the photo patternable low-k dielectric material and removing the photo patternable low-k dielectric material in unwanted regions, wherein the resulting patterned photo patternable low-k dielectric material covers the end functionalized carbon nanotubes that bridge between an assembly region in the first column and a proximate assembly region in the second column, and removing any end functionalized carbon nanotubes that are not covered by the patterned photo patternable low-k dielectric material.
 34. The method of claim 32 wherein the assembly regions comprise a metal that is selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.
 35. The method of claim 32 wherein the assembly regions comprise polysilicon or doped polysilicon.
 36. The method of claim 32 wherein the end functionalized carbon nanotubes are functionalized with amine groups.
 37. The method of claim 32 wherein the end functionalized carbon nanotubes are functionalized with Ni₃S₂NiS₂ or Co₉S₈.
 38. A structure comprising, a substrate having a surface, at least two assembly regions disposed on the substrate surface, wherein the assembly regions comprise polysilicon or doped polysilicon and carbon, nitrogen, and oxygen, a carbon nanotube wherein the carbon nanotube has ends and wherein a first end is in contact with a first assembly region and a second end is in contact with a second assembly region, and source and drain regions wherein the source region is in contact with a first end of the one or more carbon nanotubes and the drain region is in contact with the second end of the one or more carbon nanotubes.
 39. The device of claim 38 wherein the substrate additionally comprises a gate dielectric region and a gate electrode region wherein the gate dielectric region is proximate to the one or more carbon nanotubes and the gate dielectric region is between the one or more carbon nanotubes and the gate electrode region.
 40. The device of claim 38 wherein a gate dielectric material is disposed on the carbon nanotube and a gate electrode is disposed on the gate dielectric material.
 41. The device of claim 38 wherein the carbon nanotube is a single-walled semiconducting carbon nanotube.
 42. The device of claim 38 wherein a photo patternable low-k dielectric material is disposed on the carbon nanotube.
 43. A structure comprising, a substrate having a surface wherein the surface has a dielectric material disposed thereon, a via in the dielectric material. an assembly region disposed on the substrate surface at a first end of the via, wherein the assembly region comprises polysilicon or doped polysilicon and carbon, nitrogen, and oxygen, at least one carbon nanotube wherein the at least one carbon nanotube has ends, wherein one end of the at least one carbon nanotube is in contact with the assembly region and another end of the carbon nanotube is proximate to a second end of the via that is opposite to the first end of the via, a conducting region disposed at the second end of the via and in electrical contact with the carbon nanotube.
 44. The device of claim 43 wherein the at least one carbon nanotube is a bundle of carbon nanotubes.
 45. The device of claim 43 wherein the at least one carbon nanotube is a single-walled metallic carbon nanotube.
 46. The device of claim 43 additionally comprising a liner layer between the conducting region and the carbon nanotube. 